To fuel a continued trend toward further miniaturization, the electronics industry continues to research materials having a lower effective oxide thickness (“EOT”) and lower leakage. These materials potentially enable thinner and smaller area capacitors and other high-K devices used en masse in many modern circuit designs (e.g., memory arrays). Generally, the higher “K-value” (i.e., dielectric constant) a material provides, the lower the obtainable EOT. However, as dielectric layers become thinner, leakage increases, thereby inhibiting further effective miniaturization. Industry has therefore sought alternative designs to alleviate this bottleneck.
High work function metals such as platinum and ruthenium can reduce leakage, and thus are promising candidates for use as electrodes in combination with high K-value materials. However, these metals are generally much more expensive than the more common electrode materials such as titanium nitride. In addition, ruthenium in particular usually presents a strong nucleation delay issue, which further increases cost (both in terms of lost productivity and precursor cost). To elaborate on this issue, semiconductor deposition processes sometimes call for depositing a metal or metal oxide on patterned surfaces, with the desired result that the material is adhered to different types of surface geometries or substances (such as a silicon substrate or another material). Conventional ruthenium processes may present nucleation delay issues, especially where silicon or silicon oxide is involved, meaning that time and materials may be wasted in ruthenium processes, which further complicates the expense issue.
What is needed is a semiconductor stack and related method of manufacture that addresses the aforementioned problems. The present invention satisfies these needs and provides further, related advantages.